Recognizing chaotic activity during the event data pre-processing phase
Abstract
By extracting knowledge from event data, process mining tries to get insights into corporate processes. Indeed, the quality of events is an important factor in developing process models that match business process reality. To that end, pre-processing approaches have emerged to cleanse events of defects (noise, incompleteness, and rare behaviours) at the limit of chaotic activity formation. In the process, chaotic actions are carried out randomly, affecting the quality of found models. In addition, a supervised learning strategy employing labelled samples to detect chaotic behaviours has been presented. This highlights the difficulties of characterising chaotic activities in the absence of prior knowledge about which activities are actually chaotic. To that aim, we design a method for recognising chaotic events in the absence of labelled training data.
References
Gupta, K., & Jiwani, N. (2021). A systematic Overview of Fundamentals and Methods of Business Intelligence. International Journal of Sustainable Development in Computing Science, 3(3), 31-46. Retrieved from https://www.ijsdcs.com/index.php/ijsdcs/article/view/118
Momen, Mohammad Abdul. "FPGA-Based Acceleration of Expectation Maximization Algorithm using High Level Synthesis." MASc Thesis, University of Windsor, 2017.
Yixing Li, Zichuan Liu, Kai Xu, Hao Yu, and Fengbo Ren. 2018. A GPU Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks. J. Emerg. Technol. Comput. Syst. 14, 2, Article 18 (July 2018), 16 pages.
Kaiyuan Guo, Shulin Zeng, Jincheng Yu, Yu Wang, and Huazhong Yang. 2019. [DL] A Survey of FPGA-based Neural Network Inference Accelerators. ACM Trans. Reconfigurable Technol. Syst. 12, 1, Article 2 (March 2019), 26 pages.
Pawan Whig and S. N. Ahmad, On the Performance of ISFET-based Device for Water Quality Monitoring. Int'l J. of Communications, Network and System Sciences (IJCNS) (Nov 2011) ISSN (ONLINE): 1913-3715, ISSN (PRINT):1913-3723, Vol 4 pp: 709-719.
Pawan Whig and S. N. Ahmad, DVCC based Readout Circuitry for Water Quality Monitoring System, International Journal of Computer Applications (IJCA) ISBN : 973-93-80869-71-6,Volume 49 pp: 1-7.
Pawan Whig and S. N. Ahmad, A CMOS Integrated CC-ISFET Device for Water Quality Monitoring, International Journal of Computer Science Issues ,Volume 9, Issue 4, July 2012, ISSN (online): 1694-0814 pp: 365-371.
Pawan Whig and S. N. Ahmad, Performance Analysis of Various Readout Circuits for Monitoring Quality of Water Using Analog Integrated Circuits, International Journal of Intelligent Systems and Applications (IJISA) ISSN: 2074-904X (Print), ISSN: 2074-9058 (Online) Volume 4, No.11, October 2012 pp:91-98.