Fixed-Point and Floating-Point Representations in FPGA Implementations for Chaotic Maps

Abstract

One-dimensional and two-dimensional chaotic maps are implemented in this work along with other types of chaotic maps. The mathematical descriptions of the maps are altered in order to be more precisely expressed by various binary representations in order to implement them. In order to establish at what iteration various descriptions result in identical outputs, the sequences from the same map are compared. Five percent is used to establish the similarity coefficient. One intriguing result of comparison is the relative amount of comparable iterations of one-dimensional maps in this study. The bi-dimensional maps exhibit the lowest and maximum numbers of related iterations, respectively. The VHDL implementations are created using the changed mathematical descriptions. When their simulation results are compared to those of the amended mathematical description, both groups are shown to be equal.