Use of a cycle-based technique to speed up VHDL simulation

Abstract

Although the cycle-based approach is particularly effective at simulating synchronous designs, it is limited to synchronous designs and is less precise than the event-driven algorithm. A revamped cycle-based approach is suggested and put into practise in the VHDL simulator in this work. Event-driven simulation engines and cycle-based simulation engines, which may be used for synchronous and asynchronous design, respectively, have been integrated into the same simulation environment. As a result, the simulation performance is enhanced without sacrificing the event-driven algorithm's adaptability and precision.